CMOS Design of Group Delay Equaliser

Two new current-mode allpass sections based on dual-output OTAs and triple-output OTAs and grounded capacitors are described. Techniques to minimise the equaliser active device count and efficiently simulate grounded resistors are proposed. A 5th-order group delay equaliser based on the presented allpass sections is designed and simulated using multiple-output CMOS OTAs. Numerical optimisation is used to determine the equaliser order and parameters. SPICE simulation results are given demonstrating that the equaliser can effectively compensate the delay characteristic of 4th-order 4MHz lowpass Chebyshev filter to <8ns ripple over 90% of the filter passband