CLEO: Science and Innovations, CLEO_SI 2017, San Jose, California, 14-19 May 2017We experimentally demonstrate an effective hybrid equalizer with FFE and truncated Volterra filter for a 50-Gb/s PAM-4 over 50-km SSMF in a DML-based IM/DD system. The results show significant computational complexity savings without performance degradation.Department of Electronic and Information Engineering2016-2017 > Academic research: refereed > Refereed conference paperbcw
We experimentally demonstrate 112-Gbit/s PAM-4 over 80 km SSMF at 1550 nm. It is shown, that a chann...
A high-speed serial interface is the core IP of a high-performance computer, data center and interco...
DoctorTo ease high-speed link design by resolving conflicting design requirements (high-speed, low p...
We investigate the performance and implementation complexity of different equalization techniques co...
The signal in channels with high-speed designs is attenuated by channel loss, inter-symbol interfere...
We report experimental validations of an adaptive 2nd order Volterra equalization scheme for cost ef...
This dataset supports the publication: Yang Hong, Stavros Deligiannidis, Natsupa Taengnoi, Kyle R...
We demonstrate 84-Gb/s four-level pulse amplitude modulation (PAM-4) over up to 1.6-km standard sing...
Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, p...
The explosion of personal devices that need ubiquitous connectivity is making both wireless and wire...
This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS ...
The aim of this thesis to demonstrate net signal rates of 1 TB/s and 1.8 TB/s, respectively, for 16-...
International audienceWe evaluated here the positive impact of MMSE equalizers on 50Gbit/s HS-PONs. ...
We experimentally demonstrate 112-Gbit/s PAM-4 over 80 km SSMF at 1550 nm. It is shown, that a chann...
A high-speed serial interface is the core IP of a high-performance computer, data center and interco...
DoctorTo ease high-speed link design by resolving conflicting design requirements (high-speed, low p...
We investigate the performance and implementation complexity of different equalization techniques co...
The signal in channels with high-speed designs is attenuated by channel loss, inter-symbol interfere...
We report experimental validations of an adaptive 2nd order Volterra equalization scheme for cost ef...
This dataset supports the publication: Yang Hong, Stavros Deligiannidis, Natsupa Taengnoi, Kyle R...
We demonstrate 84-Gb/s four-level pulse amplitude modulation (PAM-4) over up to 1.6-km standard sing...
Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, p...
The explosion of personal devices that need ubiquitous connectivity is making both wireless and wire...
This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS ...
The aim of this thesis to demonstrate net signal rates of 1 TB/s and 1.8 TB/s, respectively, for 16-...
International audienceWe evaluated here the positive impact of MMSE equalizers on 50Gbit/s HS-PONs. ...
We experimentally demonstrate 112-Gbit/s PAM-4 over 80 km SSMF at 1550 nm. It is shown, that a chann...
A high-speed serial interface is the core IP of a high-performance computer, data center and interco...
DoctorTo ease high-speed link design by resolving conflicting design requirements (high-speed, low p...