Studies on all-optical deflection routing for all-optical packet-switched networks by using fabry-perot laser diodes for all-optical header processing

xiii, 158 p. : ill. ; 31 cm.PolyU Library Call No.: [THS] LG51 .H577P EIE 2008 LeeIn this work, we present recent investigations in all-optical packet switching. We demonstrated experimentally that packets with binary-encoded address can be switched optically with all-optical bitwise header processing by using Fabry-Perot laser diodes. We then carried out experiments to show that packet contention can be re-solved ail-optically by using deflection routing in a 2x2 switch. We then demonstrated theoretically that NxN deflection routing node can be constructed using the 2x2 deflection routing nodes as building blocks. Since the performance of a deflection routing node can be significantly enhanced even with the use of very limited buffers, we also have investigated experimentally the feasibility of all-optically buffer. In previous work by members of our research group, we have shown that a packet-long control signal can be generated based on the interaction at a single bit interval at the packet header by using the bistability and multimode injection locking properties of a Fabry-Perot laser diode (FP-LD). We demonstrated all-optical on-off switching of packets with all-optical header processing using a FP-LD as header processor. We also demonstrated all-optical add/drop of packets based on the same principle. In order to simplify the demand on optical signal processing, we have adopted in our previous work a novel self-routing address format (also proposed by our group) in which every output port of all the nodes in a network is identified by a single bit in the address. Thus the length of the address is proportional to the size of the network. The length of the bit-wise address proposed will become a problem if the network size increases, hi this thesis, in order to shorten the address length I demonstrated that packets with binary-encoded address can be properly routed ail-optically by using multi-wavelength cross-gain modulation property of semiconductor optical amplifiers and multimode injection locking of FP-LDs. The length of the address can therefore be reduced from N to log₂N bits where N is the total number of output ports of all the nodes in the network. The number of FP-LDs required is also reduced to log₂N. In this demonstration, output port contentions by the packets are not considered.We then studied the use of deflection routing to resolve packet contention problem. We simplified the experimental setups by using the novel self-routing addresses for the packet header rather than the binary addresses. We considered a 2x2 node which consists of a header extractor, a header processor, a 2x2 Cross/Bar switching cell, and an add/drop module. The contention resolution strategy is encoded in the switch configuration: when both packets want to exit the same port, the 2x2 Cross/Bar switch will be set to the Bar state. We then demonstrated theoretically that an NxN deflection routing node can be constructed using the demonstrated 2x2 deflection routing nodes. Header comparators unit are used to erase all but one of the packets headers for packets with identical headers. Then we also discussed how to implement deflection preferences which can be used to in conjunction with the novel self routing addresses. It is well-known that the throughput-delay performance of deflection routing network can be significantly improved by adding buffer, even with very limited capability, to the nodes of the network. We therefore study all-optical buffers and demonstrated that an optically controlled memory using a photonic crystal fiber based nonlinear optical loop mirror for all-optical packet-switched networks. The 10 Gb/s data can be stored in the buffer up to a period of 2.5 μs. We use the cross phase modulation property between the control signal and the data signal to store and retrieve data packets in the memory. Packet contention problem can be solved by storing the contented data packets in the memory and retrieving them for transmission in the next time slot.Department of Electronic and Information EngineeringPh.D., Dept. of Electronic and Information Engineering, The Hong Kong Polytechnic University, 200