Design and implementation of a hardware unit for complex division

The purpose of the thesis was to investigate and evaluate existing algorithms for division of complex numbers. The investigation should include implementation of a few suitable algorithms in VHDL. The main application for the divider is compensation for fading in a baseband processor. Since not much public research is done within the area of complex division in hardware, a divider based on real valued division was designed. The design only implements inversion of complex numbers instead of complete division because it is simpler and the application does not need full division, thus the required chip size is reduced. An examination of the different kinds of algorithms that exists for real valued division was done and two of the methods were found suitable for implementation, digit recurrence and functional iteration. From each of the two classes of algorithms one algorithm was chosen and implemented in VHDL. Two different versions of the inverter were designed for each method, one with full throughput and one with half throughput. The implementations show very similar results in terms of speed, size and performance. For most cases however, the digit recurrence implementation has a slight advantage