Beteendemodell for DSP-processor med skalbar struktur

In mobile digital devices, low power consumption is an important matter to reduce the need for a heavy and big battery. One way of reducing the power consumption is to construct the hardware so that the performance is optimal for the application. The demand of performance is dependent of the tasks that the device will be performing. This is where scalable structure of the hardware is an idea to solve the problem. This master thesis serve as a starting point for developing a digital signal processor with scalable structure. The digital signal processor is a common and important part of digital processing. Scalable struture is in this case adding and removing parts of the memory and/or the instruction set, and to make the data wordlength variable. The development is simplified by modeling it on an existing processor. The result of this master thesis is an instruction simulator written in C language. The simulator will be a model for development of the hardware