Defect states characterization of non-annealed and annealed ZrO2/InAlN/GaN structures by capacitance measurements

InAlN/GaN metal-oxide-semiconductor structures with non-annealed and annealed ZrO2 gate insulators were characterized by capacitance-voltage (C-V) measurements. A significant capacitance hysteresis in both channel depletion and barrier accumulation regions was observed on the non-annealed structures. Fixed positive charge in the gate insulator was identified from the negative shift of the C-V curves. The C-V hysteresis was negligible and the threshold voltage decreased with a corresponding increase of the sheet charge density by 6 x 10(12) cm(-2) after annealing. The C-V slope in the accumulation region increased and the flat-band voltage decreased with decreased frequency. This confirms a decrease of the oxide/barrier interface trap state density with increased their activation energy. Capacitance saturation in the accumulation region occurs at lower values than it is in the insulator capacitance. Measurements at increased temperature up to 150 degrees C show a shift of the flat-band voltage to lower values. Both facts support an explanation that leakage current through the gate insulator occurs in the barrier accumulation region. This shows that evaluation of the trap states density from this part of the C-V curves might be difficult. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4792060