In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) wit...
DoctorRecently, the conventional planar MOSFET is caught on the barrier scaling to sub 22 nm technol...
In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-cu...
In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies ...
This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n...
The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-M...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In this paper, we report the first systematic study on electron mobility extraction in equilateral t...
Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers push...
In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V ch...
We present experimental results on on-current and transconductance gain and mobility enhancement in ...
In the era of portable electronic devices energy efficient integrated circuits (ICs) are highly dema...
Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-e...
For the past couple of decades the desire to add more complexity to a computer chip, while simultane...
In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm S...
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) wit...
DoctorRecently, the conventional planar MOSFET is caught on the barrier scaling to sub 22 nm technol...
In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-cu...
In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies ...
This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n...
The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-M...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In this paper, we report the first systematic study on electron mobility extraction in equilateral t...
Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers push...
In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V ch...
We present experimental results on on-current and transconductance gain and mobility enhancement in ...
In the era of portable electronic devices energy efficient integrated circuits (ICs) are highly dema...
Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-e...
For the past couple of decades the desire to add more complexity to a computer chip, while simultane...
In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm S...
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) wit...
DoctorRecently, the conventional planar MOSFET is caught on the barrier scaling to sub 22 nm technol...
In this work, strained Si (sSi) nanowire array of n-TFETs with gates all around (GAA) yielding ON-cu...