Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation o...
Reconfigurable platforms are a promising technology that offers an interesting trade-off between fle...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable ...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to the...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
We consider the problem of scheduling the operations of a data flow graph in a reconfigurable comput...
Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation o...
Reconfigurable platforms are a promising technology that offers an interesting trade-off between fle...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in ...
High-performance reconfigurable computing involves acceleration of significant portions of an ap-pli...
New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable ...
In this paper we present a novel scheduling technique for partially-reconfigurable FPGA-based system...
Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to the...
In this dissertation, we focus our research on the problems related to efficient configurable resour...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
We consider the problem of scheduling the operations of a data flow graph in a reconfigurable comput...
Reconfigurable hardware can be used to build multi tasking systems that dynamically adapt themselves...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...