Growing core counts have highlighted the need for scalable on-chip coherence mechanisms. The increase in the number of on-chip cores exposes the energy and area costs of scaling the directories. Duplicate-tag based directories require highly associative structures that grow with core count, precluding scalability due to prohibitive power consumption. Sparse directories overcome the power barrier by reducing directory associativity, but require storage area over-provisioning to avoid high invalidation rates. We propose the Cuckoo directory, a power- and area-efficient scalable distributed directory. The cuckoo directory scales to high core counts without the energy costs of wide associative lookup and without gross capacity over-provisioning...
URL to conference programIn the many-core era, scalable coherence and on-chip interconnects are cruc...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high sy...
A key challenge in architecting a multicore processor is efficiently maintaining cache coherence. Di...
Conventional directory coherence operates at the finest granularity possible, that of a cache block....
As the number of cores increases in both incoming and future shared-memory chip--multiprocessor (CMP...
Although directory-based cache coherence protocols are the best choice when designing chip multiproc...
Directories used for cache coherence are vulnerable to side channel attacks. Directories are inclusi...
To support legacy software, large CMPs often provide cache coherence via an on-chip directory rathe...
As the number of cores increases in both incoming and future chip multiprocessors, coherence proto...
Abstract. If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced...
We introduce the concept of deadlock-free migration-based coherent shared memory to the NUCA family ...
With increasing core counts, the scalability of directory-based cache coherence has become a challen...
In this paper, we propose an effortless way for disaggregating the CPU-memory couple, two of the mos...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
URL to conference programIn the many-core era, scalable coherence and on-chip interconnects are cruc...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high sy...
A key challenge in architecting a multicore processor is efficiently maintaining cache coherence. Di...
Conventional directory coherence operates at the finest granularity possible, that of a cache block....
As the number of cores increases in both incoming and future shared-memory chip--multiprocessor (CMP...
Although directory-based cache coherence protocols are the best choice when designing chip multiproc...
Directories used for cache coherence are vulnerable to side channel attacks. Directories are inclusi...
To support legacy software, large CMPs often provide cache coherence via an on-chip directory rathe...
As the number of cores increases in both incoming and future chip multiprocessors, coherence proto...
Abstract. If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced...
We introduce the concept of deadlock-free migration-based coherent shared memory to the NUCA family ...
With increasing core counts, the scalability of directory-based cache coherence has become a challen...
In this paper, we propose an effortless way for disaggregating the CPU-memory couple, two of the mos...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
URL to conference programIn the many-core era, scalable coherence and on-chip interconnects are cruc...
Nowadays, most computer manufacturers offer chip multiprocessors (CMPs) due to the always increasing...
Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high sy...