3D stacked architectures reduce communication delay in multiprocessor system-on-chips (MPSoCs) and allowing more functionality per unit area. However, vertical integration of layers exacerbates the reliability and thermal problems, and cooling is a limiting factor in multi-tier systems. Liquid cooling is a highly efficient solution to overcome the accelerated thermal problems in 3D architectures. However, liquid cooling brings new challenges in modeling and run-time management. This paper proposes a design-time/run-time thermal management policy for 3D MPSoCs with inter-tier liquid cooling. First, we perform a design-time analysis to estimate the thermal impact of liquid cooling and dynamic voltage frequency scaling (DVFS) on 3D MPSoCs. Bas...
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlik...
3D stacked wafer integration has the potential to improve multipro-cessor system-on-chip (MPSoC) int...
Process technologies are approaching physical limits making further reduction of device size and hig...
Abstract — 3D stacked architectures reduce communication delay in multiprocessor system-on-chips (MP...
3D stacked systems reduce communication delay in multiprocessor system-on-chips (MPSoCs) and enable ...
In this work, we propose a novel online thermal management approach based on model predictive contro...
Vertically-integrated 3D multiprocessors systems-on-chip (3D MPSoCs) provide the means to continue i...
Rising chip temperatures and aggravated thermal reliability issues have characterized the emergence ...
Abstract — Three-dimensional (3D) circuits reduce communication de-lay in multicore SoCs, and enable...
Three-dimensional (3D) stacking is an attractive method for designing large manycore chips as it pro...
International audience3D stacked architectures are getting increasingly attractive as they improve y...
Abstract—Liquid cooling has emerged as a promising solution for addressing the elevated temperatures...
Abstract—3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enab...
While possessing the potential to replace conventional air-cooled heat sinks, inter-tier microchanne...
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlik...
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlik...
3D stacked wafer integration has the potential to improve multipro-cessor system-on-chip (MPSoC) int...
Process technologies are approaching physical limits making further reduction of device size and hig...
Abstract — 3D stacked architectures reduce communication delay in multiprocessor system-on-chips (MP...
3D stacked systems reduce communication delay in multiprocessor system-on-chips (MPSoCs) and enable ...
In this work, we propose a novel online thermal management approach based on model predictive contro...
Vertically-integrated 3D multiprocessors systems-on-chip (3D MPSoCs) provide the means to continue i...
Rising chip temperatures and aggravated thermal reliability issues have characterized the emergence ...
Abstract — Three-dimensional (3D) circuits reduce communication de-lay in multicore SoCs, and enable...
Three-dimensional (3D) stacking is an attractive method for designing large manycore chips as it pro...
International audience3D stacked architectures are getting increasingly attractive as they improve y...
Abstract—Liquid cooling has emerged as a promising solution for addressing the elevated temperatures...
Abstract—3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enab...
While possessing the potential to replace conventional air-cooled heat sinks, inter-tier microchanne...
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlik...
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlik...
3D stacked wafer integration has the potential to improve multipro-cessor system-on-chip (MPSoC) int...
Process technologies are approaching physical limits making further reduction of device size and hig...