Analysis of Error Recovery Schemes for Networks on Chips
- Murali, Srinivasan
- Benini, Luca
- Theocharides, Theocharis
- Vijaykrishnan, N.
- Irwin, Mary Jane
- De Micheli, Giovanni
Publication date
November 2005
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms
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