Development of a Predictable Hardware Architecture Template and Integration into an Automated System Design Flow

The requirements of safety-critical real-time embedded systems pose unique challenges on their design process which cannot be fulfilled with traditional development methods. To ensure their correct timing and functionality, it has been suggested to move the design process to a higher abstraction level, which opens the possibility to utilize automated correct-by-design development flows from a functional specification of the system down to the level of Multiprocessor Systems-on-Chip (MPSoCs). ForSyDe, an embedded system design methodology, presents a flow of this kind by basing system development on the theory of Models of Computation and side-effect-free processes, making it possible to separate the timing analysis of computation and communication of process networks. To be able to offer guarantees on the timing of tasks implemented on a MPSoc, the hardware platform needs to provide predictability and composability in every component, which in turn requires a range of special considerations in its design. This thesis presents a predictable and composable FPGA-based MPSoC template based on the Altera Nios II soft processor and Avalon Switch Fabric interconnection structure and its integration into the automated ForSyDe system design flow. To present the functionality and to test the validity of timing predictions, two sample applications have been developed and tested in the context of the design flow as well as on the implemented hardware platform