Multi-Path Dierential Delay Line based Time-to-Digital Converter for ADPLL

All digital phase-locked loops (ADPLLs) play an important role in contemporary applications such as Bluetooth, GSM, WCDAM and WiFi. A timeto-digital converter (TDC) is the critical part in the ADPLL, usually the dominant quantization noise contributor. The quantization noise is caused by the nite resolution of the TDC. Thus, a high resolution TDC with easy implementation (digital-friendly) feature is desired for the ADPLL. After the investigation of different existing TDC topologies, an improved TDC based on a multi-path differential delay line is proposed and designed in 65-nm CMOS process. The proposed TDC utilizes the minimal-delay inverter as the delay element and a sense amplifer ip-op as the comparator, which demonstrates high resolution and simple implementation. The TDC contains 60 delay stages and was post-layout simulated with a 25-MHz reference clock and a 4.06-GHz oscillator clock. The power consumption is 1.215-mW from a 1.2-V supply with power saving enabled. The DNL and INL are lower than 0.25 LSB. The typical resolution is around 9-ps, which meet the application spec. The TDC core layout has an area of 201:5 41:5 m2