Dessign and Implementation of Hardened Reconfiguration Controller for Self-Healing Systems on SRAM-Based FPGAs

As digital systems become large and complex, their dependability is getting more important, particularly in mission-critical and safety‐critical applications. Among various available platforms for implementing a digital system, SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly adopted in embedded systems due to their flexibility in achieving multiple requirements such as low cost, high performance, and fast turnaround time compared to Fixed Application Specific Integrated Circuits (ASICs). The most attractive feature of SRAM-based FPGAs is the ability of re‐programming1 the device in a few clock cycles. This feature is further enhanced by the introduction of Partial Dynamic Reconfiguration (PDR). PDR allows reconfiguration partially and on the fly, while the device is operating. Nevertheless, SRAM-based FPGAs are more susceptible to faults compared to other type of FPGAs and ASICs. One of these faults, which mostly happen in higher altitude2, is bit flop in configuration memory caused by ionizing radiation. If this bit flop alters the critical bits3 in the configuration memory, the function of the design can be corrupted. Thus, appropriate hardening techniques should be used in order to increase device dependability. In general, fault tolerant techniques are mostly based on spatial redundancy. However, these techniques can be combined with FPGA’s re-configuration capability for recovery. Since the complexity of systems is increasing and utilizing hardening techniques demand higher resources, a single FPGA may not suffice to contain whole system. In this case, multi-FPGA platforms would be taken into account. In this thesis, a hardened generic reconfiguration controller that manages the occurrence of soft-errors in self-healing systems implemented on SRAM‐based FPGAs is demonstrated and analyzed. The controller shows the ability to correct the SEUs in the configuration memory - in both static and partial reconfigurable regions - by means of Xilinx PDR capability. Moreover, the controller, itself, is hardened with fault-tolerant techniques and it is able to detect and mask its own errors. The developed controller is compared with similar approaches based on micro-controller inside the FPGA. Eventually, the presented structure is proven fully functional on XUPV5-LX110T evaluation board