Design of oversampling current steering DAC with 640MHz equivalent clock frequency

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references (leaves 59-62).Issued also on microfiche from Lange Micrographics.A DAC (Digital-to-Analog Converter) architecture based on the current steering method is proposed. The architecture exploits the first order sigma-delta modulator, oversampling technique, multi-bit and MASH (multi stage noise shaping) configuration. The DAC adopted MASH structure requires two current steering 6-bit D/A converters whose current references are properly scaled. The two output currents are combined at the output node to achieve the output signal. For high frequency operation, we modified sigma-delta structure to parallel four paths digital sigma-delta modulator by concerning the data stream in the conventional sigma-delta architecture. Each path has the 160MHz-clock frequency so that total output data stream can work at 640MHz-clock frequency. Since the DAC employs multi-bit solution, the dynamic matching of element technique is applied to current cells in the DAC. Rotated data weight averaging algorithm, one of the matching techniques, is used for mismatch error reduction. The DAC operates with an oversampling factor equal to 8 and 40 MHz band-width (clock frequency 640 MHz) and the possible output SNR (signal-to-noise ratio) reaches an SNR as large as 86 dB