Implementation of a low power adaptive binary encoder

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references (leaves 79-81).Issued also on microfiche from Lange Micrographics.The demand for a low power implementation of a data compression technique is driven by the need for small, light-weight portable electronic devices that need to operate on battery power for extended periods of time at reasonable frequencies. The circuit idea presented sets forth a method to assist a device in meeting these demands through the use of an adaptive binary encoder that operates at desirable frequencies and takes up a minimal amount of space either as a stand alone component or when implemented as a small part of a larger system on a chip. The circuit presented is capable of compressing a continuous parallel stream of symbols into a serial stream of codewords that are compressed based on the recent history of the symbols that have passed through the encoder. The encoder was designed with a focus on implementation in silicon in a low power environment