Yield learning with line width, sample size and bridge resistance variation

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references: p. 101-106.Issued also on microfiche from Lange Micrographics.Rapid failure analysis and continuous monitoring of the fabrication line are required in order to maximize the slope of the semiconductor manufacturing yield ramp. Metrology costs are the fastest rising expense occurring in the fabrication line. In addition, many of the defects can only be detected using electrical methods. Hence the use of simulation-based models for defect diagnosis is on the increase. We have used an already available methodology of defect-fault dictionary building and have observed the effects of certain noise sources such as line width variation, sample size and bridge resistance on yield learning, and determined how to account for them. In this research we will show that since line width variation is not random on a few wafer samples, its effect on defect Pareto predictions is profound and must be collected. We will show that a linear model is sufficient to correct for the sensitivity of defect density to line width variation and shall also confirm this experimentally. We have examined the effect of various defect sample sizes on the resolution of the defect-fault dictionary and hence on the diagnosibility. We will show that the dictionary construction costs can be reduced by using relatively small sample sizes without a significant reduction in Pareto accuracy. We shall also show that a distribution of bridge resistance does not effect the Pareto accuracy. Our observations and correction model allow us to make accurate defect Pareto predictions in the presence of these noise sources