Comprehensive functional testing and dynamic compensation techniques for Cellular Neural Networks

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references.Issued also on microfiche from Lange Micrographics.Cellular Neural Networks (CNN's) are analog, non-linear, dynamic systems which are especially well suited for solving problems in the areas of image processing and pattern recognition. State of the art implementations of two-dimensional CNN's arrays are fabricated in sub-micron Very Large Scale Integration (VLSI) technologies. The increase in circuit integration has driven the need to develop robust testing methods to establish baseline functionality of CNN'S. Present techniques for testing CNN hardware provide only limited capabilities, often require additional hardware, and are limited to specific topologies. The goal of this thesis is to provide a deterministic method to conduct functional testing and dynamic compensation of CNN arrays independent of the size or topology of the array. The methods provide comprehensive, non-invasive techniques for verifying the integrity of each of the functional paths as well as procedures to measure and minimize parametric faults in real CNN hardware. The functional tests consist of a sequence of inputs to the array that insure each node in the system level representation of the CNN is toggled and propagated to the output where it is compared to a known good output vector set. The dynamic compensation strategies characterize and attempt to minimize or eliminate the effect of undesirable parametric faults such as time-constant mismatches, non-linearity in the multipliers and state nodes, and system offsets. Whenever possible, the compensation techniques are carried out locally on each cell independently, otherwise a global compensation approach is used. Numerous CNN architectures had to be modeled to provide insight into different problems faced when testing a VLSI implementations of CNN arrays. For this reason, a set of software tools was developed to select CNN macromodels of different complexities, combine input stimulus files in a logical manner, and generate the necessary files for simulation. The simulation results were used to design, refine, and measure the effectiveness of the proposed testing strategies