Design of a 6-bit DAC 4 Gs/s in 90-nm CMOS

Abstract This thesis focuses on the design of a 6-bit current steering Digital-to-Analog Converter (DAC) with 4 GHz clock frequency. The circuit is designed in ST Microelectronic CMOS090, 90nm process, with a supply voltage of 1.2 V. The design is based on a differential current steering topology. The differential output of the DAC is loaded with the two 50 Ω resistors and a full-scale differential voltage of 300 mVpp is generated. The unit current cell is designed for a 2/4 thermometer/binary segmented DAC. The simulated DAC converts two most significant bits (MSBs) into the thermometer code, which controls the 48 unit current sources, 16 for each MSB. The remaining four least significant bits (LSBs) control four binary-scaled current sources, each one with 8, 4, 2, 1 unit current sources respectively. In this design a 2-bit binary to 3-bit thermometer decoder is used. Several current cell topologies are compared with respect to traditional problems associated with the current cell design. Cascoding is demonstrated being the best option to overcome the error sources associated with the unit current cell design. However, the low supply voltage of 1.2 V in CMOS090 limits the cascoding benefits. In this thesis, the design and sizing of unit current source and the problems related to digital part are studied. From this a full custom circuit is laid out