Efficient low latency techniques and VLSI architectures for LDPC codes decoding

Low Density Parity Check (LDPC) codes are block linear forward error correction codes ideal for modern high data rate communication standard as the upcoming IEEE 802.11n for high throughput WLAN. For such applications defining an efficient low latency, or dually high throughput, HW decoder architecture is a key issue. The decoding process runs iteratively in application of the maximum a posteriori algorithm formulated in the form of belief propagation. Aiming at reducing the decoding latency the adoption of fast convergence schedules, as the layered one, can even halve the number of the iterations required to meet a target error correction performance. As a drawback the use of such schedules creates, within the same iteration, a time dependency between the operations usually resulting into a memory conflict. This dependency spoils the efficiency of classic pipelined decoder architectures leading again to an increase of the decoding latency. To counteract this problem algorithm approximations can be adopted but to the detriment of code performance. This work proposes new techniques to minimize the iteration latency for layered decoder without affecting the convergence speed neither the error correction features. According to the particular architecture of the processing units the sequence of the elaborations is scheduled such that the occurrence of the memory conflicts is minimized and, when it is not avoidable, a minimum number of idle cycles is introduced in the elaborations temporarily interrupting the pipeline. Different VLSI architectures to fit the minimum latency strategies are then proposed and compared showing different trade–off between decoder complexity and performance. As a case example the complete design flow is applied to the IEEE 802.11n codes showing remarkable results when compared to the state–of–the–art