This is a preliminary study in which we use a genetic algorithm to solve the multiple layer floorplanning problem. The original contribution is a three dimensional slicing structure representation which, to the best of our knowledge, is the first 3D floorplan representation in the literature. In this paper we give some background on VLSI design and the floorplanning problem before describing the slicing structure representation\ud and the genetic algorithm extensions. We present results for benchmark problems and obtain improvements on previously published results for single layer floorplanning
The building blocks in a given floor-plan may have several possible physical implementations yie1din...
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this pape...
Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorpl...
The design of a manufacturing layout is incomplete without consideration of aisle structure for mate...
We present a genetic algorithm (GA) which used a normal- ized postfix encoding scheme to solve the ...
Floorplanning is one of the most important problems in VLSI physical design automation. A fundamenta...
As the impact of interconnect on IC performance and chiparea in deep submicron design increases, res...
Floorplanning is one of the most important problems in VLSI physical design automation. A fundamenta...
We present a genetic algorithm (GA) that uses a slicing tree construction process for the placement ...
Dramatic improvements in circuit integration technologies have resulted in a huge increase in the co...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
Abstract:- With resent advances of Deep Sub Micron technologies, the floorplanning problem is an ess...
Slicing tree has been an effective tool for VLSI floorplan de-sign. Floorplanners using slicing tree...
[[abstract]]We consider in this paper the problem of slicing floorplan design with boundary-constrai...
Genetic Algorithms are search oriented empirical techniques, which are derived from the Theory of Na...
The building blocks in a given floor-plan may have several possible physical implementations yie1din...
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this pape...
Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorpl...
The design of a manufacturing layout is incomplete without consideration of aisle structure for mate...
We present a genetic algorithm (GA) which used a normal- ized postfix encoding scheme to solve the ...
Floorplanning is one of the most important problems in VLSI physical design automation. A fundamenta...
As the impact of interconnect on IC performance and chiparea in deep submicron design increases, res...
Floorplanning is one of the most important problems in VLSI physical design automation. A fundamenta...
We present a genetic algorithm (GA) that uses a slicing tree construction process for the placement ...
Dramatic improvements in circuit integration technologies have resulted in a huge increase in the co...
The first stage in hierarchical approaches to floorplan design determines certain topological relati...
Abstract:- With resent advances of Deep Sub Micron technologies, the floorplanning problem is an ess...
Slicing tree has been an effective tool for VLSI floorplan de-sign. Floorplanners using slicing tree...
[[abstract]]We consider in this paper the problem of slicing floorplan design with boundary-constrai...
Genetic Algorithms are search oriented empirical techniques, which are derived from the Theory of Na...
The building blocks in a given floor-plan may have several possible physical implementations yie1din...
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this pape...
Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorpl...