Add to ORKGWe employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuristics are based on Genetic Algorithms (GA's) and Tabu Search (TS)[1] respectively. We address a multiobjective version of the problem in which, power dissipation, timing performance, and interconnect wire lenghth are optimized while layout width is taken as a constraint. Fuzzy rules are incorporated in order to design a multi-objective cost function that integrates the cost of three objectives in a single overall cost value. A series of experiments is performed to study the effect of important algorithmic parameters of GA and TS. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compar...
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to mol...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
A hybrid heuristic for multiobjective VLSI cell placement is presented, which draws from the memory ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
We engineer a well known optimization technique namely Tabu Search (TS) [1] for the performance and ...
We engineer a well-known optimization technique namely tabu search (TS) (Sait and Youssef, 1999) for...
The problem of partitioning appears in several areas ranging from VLSI parallel programming, to mole...
In this paper, an algorithm for VLSI standard cell placement for low power and high performance desi...
In this paper, an algorithm for VLSI standard cell placement for low power and high performance desi...
VLSI standard cell placement is the process of arranging circuit components (modules) on a silicon l...
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to mol...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
A hybrid heuristic for multiobjective VLSI cell placement is presented, which draws from the memory ...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
We engineer a well known optimization technique namely Tabu Search (TS) [1] for the performance and ...
We engineer a well-known optimization technique namely tabu search (TS) (Sait and Youssef, 1999) for...
The problem of partitioning appears in several areas ranging from VLSI parallel programming, to mole...
In this paper, an algorithm for VLSI standard cell placement for low power and high performance desi...
In this paper, an algorithm for VLSI standard cell placement for low power and high performance desi...
VLSI standard cell placement is the process of arranging circuit components (modules) on a silicon l...
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to mol...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
A hybrid heuristic for multiobjective VLSI cell placement is presented, which draws from the memory ...