An electromigration (EM) test mask was designed to utilize both standard ASTM and Standard Wafer-level Electromigration Accelerated Test Structures (SWEAT) fourterminal EM test structures of varying line-widths. The mask was used to pattern 4” test wafers consisting of 300 nm of sputtered aluminum-1% silicon on a thermal SiO2 layer. A custom thermal setup was developed for a Micromanipulator 6000 manual probe station. A new 4” brass chuck was machined to include cooling channels, wafer vacuum, and a thermocouple monitoring system. A resistive ring heater was bonded to the chuck and was controlled via a process temperature controller. Extensive electrical test of interconnect structures was necessary to generate EM lifetime data for the allo...
Electromigration (EM) of micro bumps of 50 μm pitch was studied using four-point Kelvin structure. T...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
The main focus is to further develop the accelerated wafer-level ISO-J and IOS-T EM tests with the...
An electromigration (EM) test mask was designed to utilize both standard ASTM and Standard Wafer-lev...
The design of a novel test structure to study the influence of electromigration and thermomigration ...
The steady state and transient thermal behavior of an electromigration test structure was analyzed. ...
This work is aimed at proposing a standard procedure for moderately accelerated Electromigration (EM...
To accommodate the increasing input-out (I/O) counts in future integrated circuits, the size of the ...
Microelectronic test structures are used for wide variety of tasks which include equipment character...
As VLSI chip sizes and packing densities continue to escalate, electromigration failures have become...
Through Silicon Via (TSV) is a hot topic in today’s 3D Integrated Circuit. In order for TSV to be us...
Pure evaporated aluminum interconnects on a flat surface and over topography were subjected to high ...
Further miniaturization of electronic systems is approaching new limits due to the failure mechanism...
Electromigration is the mass transport of atoms in a material due to elevated temperatures and an ap...
Electromigration tests have been performed on a number of test structures with different geometries ...
Electromigration (EM) of micro bumps of 50 μm pitch was studied using four-point Kelvin structure. T...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
The main focus is to further develop the accelerated wafer-level ISO-J and IOS-T EM tests with the...
An electromigration (EM) test mask was designed to utilize both standard ASTM and Standard Wafer-lev...
The design of a novel test structure to study the influence of electromigration and thermomigration ...
The steady state and transient thermal behavior of an electromigration test structure was analyzed. ...
This work is aimed at proposing a standard procedure for moderately accelerated Electromigration (EM...
To accommodate the increasing input-out (I/O) counts in future integrated circuits, the size of the ...
Microelectronic test structures are used for wide variety of tasks which include equipment character...
As VLSI chip sizes and packing densities continue to escalate, electromigration failures have become...
Through Silicon Via (TSV) is a hot topic in today’s 3D Integrated Circuit. In order for TSV to be us...
Pure evaporated aluminum interconnects on a flat surface and over topography were subjected to high ...
Further miniaturization of electronic systems is approaching new limits due to the failure mechanism...
Electromigration is the mass transport of atoms in a material due to elevated temperatures and an ap...
Electromigration tests have been performed on a number of test structures with different geometries ...
Electromigration (EM) of micro bumps of 50 μm pitch was studied using four-point Kelvin structure. T...
International audienceA recently proposed methodology for electromigration (EM) assessment in on-chi...
The main focus is to further develop the accelerated wafer-level ISO-J and IOS-T EM tests with the...