Design, Fabrication, and Testing of Crystalline Silicon source/ Drain FinFETs

Crystalline silicon source/drain FInFET structures were designed, fabricated, and tested at the RIT Semiconductor \u26 Microsystems Fabrication Laboratory (SMFL). Process development was completed using hand calculations, simulations, and similar processing techniques based upon mature RIT semiconductor manufacturing processes. The design under investigation is a dog-bone structure fabricated on SOT substrates. The crystalline silicon source/drain FinFETs exhibited a field effect behavior for all transistor sizes fabricated, however the smaller 1μm FinFETs were more susceptible to background noise. The smallest device, a 1x2μm FInFET yielded VT=1.53V and a drive current of 510 μA with VG=5V. The largest device, a 4x80μm FinFET yielded VT=1.42V and a drive current of 4.1 mA with VG=SV.