This project evaluated the implications of system level electro-static discharge (ESD) on a touch and display driver integrated (TDDI) architecture component. Due to the components unique location in the system, typical component level ESD standards (JEDEC Human Body Model and Charged Device Model) were unable to adequately represent the ESD stresses seen by the integrated circuit (IC) during system level ESD testing (IEC 61000-4-2). An alternative stimulus, transmission line pulse (TLP), has been purposed as a better metric to model the devices performance under system level ESD testing and ESD devices were optimized to this stimulus
This dissertation, composed of four papers, discusses three topics related to system level electrost...
Electrostatic discharge (ESD) is a major source of failures in electronic devices and products detec...
Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip dama...
This project evaluated the implications of system level electro-static discharge (ESD) on a touch an...
Goal: Evaluate component level design constraints to assist in system level electrostatic discharge ...
Chapter Two introduces into phenomena of electrostatic discharge ESD which may damage integrated cir...
Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design...
[[abstract]]Motivation of this research study is to compare the Electro Static Discharge (ESD) chara...
Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliab...
International audienceFor both Equipment Manufacturers (EM) and semiconductor suppliers, the predict...
This book addresses key aspects of analog integrated circuits and systems design related to system l...
A custom test board facilitates transmission line pulse (TLP) characterization of the external pins ...
Abstract- In the advanced deep-submicron CMOS technology, it is more difficult to prevent damages fr...
An effective and cost efficient protection of electronic system against ESD stress pulses specified ...
lectronic system designs often include transient protection to ensure system robustness for electros...
This dissertation, composed of four papers, discusses three topics related to system level electrost...
Electrostatic discharge (ESD) is a major source of failures in electronic devices and products detec...
Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip dama...
This project evaluated the implications of system level electro-static discharge (ESD) on a touch an...
Goal: Evaluate component level design constraints to assist in system level electrostatic discharge ...
Chapter Two introduces into phenomena of electrostatic discharge ESD which may damage integrated cir...
Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design...
[[abstract]]Motivation of this research study is to compare the Electro Static Discharge (ESD) chara...
Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliab...
International audienceFor both Equipment Manufacturers (EM) and semiconductor suppliers, the predict...
This book addresses key aspects of analog integrated circuits and systems design related to system l...
A custom test board facilitates transmission line pulse (TLP) characterization of the external pins ...
Abstract- In the advanced deep-submicron CMOS technology, it is more difficult to prevent damages fr...
An effective and cost efficient protection of electronic system against ESD stress pulses specified ...
lectronic system designs often include transient protection to ensure system robustness for electros...
This dissertation, composed of four papers, discusses three topics related to system level electrost...
Electrostatic discharge (ESD) is a major source of failures in electronic devices and products detec...
Electrostatic discharge (ESD) is responsible for more than 25% of semiconductor device and chip dama...