Subthreshold and gate leakage current analysis and reduction in VLSI circuits

CMOS technology has scaled aggressively over the past few decades in an effort to enhance functionality, speed and packing density per chip. As the feature sizes are scaling down to sub-100nm regime, leakage power is increasing significantly and is becoming the dominant component of the total power dissipation. Major contributors to the total leakage current in deep submicron regime are subthreshold and gate tunneling leakage currents. The leakage reduction techniques developed so far were mostly devoted to reducing subthreshold leakage. However, at sub-65nm feature sizes, gate leakage current grows faster and is expected to surpass subthreshold leakage current. In this work, an extensive analysis of the circuit level characteristics of subthreshold and gate leakage currents is performed at 45nm and 32nm feature sizes. The analysis provides several key observations on the interdependency of gate and subthreshold leakage currents. Based on these observations, a new leakage reduction technique is proposed that optimizes both the leakage currents. This technique identifies minimum leakage vectors for a given circuit based on the number of transistors in OFF state and their position in the stack. The effectiveness of the proposed technique is compared to most of the mainstream leakage reduction techniques by implementing them on ISCAS89 benchmark circuits. The proposed leakage reduction technique proved to be more effective in reducing gate leakage current than subthreshold leakage current. However, when combined with dual-threshold and variable-threshold CMOS techniques, substantial subthreshold leakage current reduction was also achieved. A total savings of 53% for subthreshold leakage current and 26% for gate leakage current are reported