A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor

The creation of a parameterized, full custom CMOS VLSI design library is discussed. This library consists of a schematic component library that is integrated with both logic and circuit level simulators, as well as a corresponding layout cell library that is integrated with automatic place-and-route tools as well as several layout verification tools. The library enabled the design and implementation of a Morphological Array Processor (MAP). This VLSI chip fully implements the morphological operations of erosion and dilation using a 7x7 matrix. It will operate on a 512x512 image in real time (60 images per second). The chip is designed to be pipelined for multiple successive morphologic operations on a series of images. The MAP is implemented using an 2.0 micrometers N-well CMOS process which can be fabricated through the MOSIS program