LOW POWER AND LOW AREA MULTIPLICATION CIRCUITS THROUGH PARTIAL PRODUCT PERFORATION

Focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. The partial product perforation method for creating approximate multipliers. It omit the generation of some partial products, thus reducing the number of partial products that have to be accumulated; we decrease the area, power. The major contributions of this work, the software-based perforation technique on the design of hardware circuits, obtaining the optimized design solutions regarding the power–area–error tradeoffs. Analyze in a mathematically rigorous manner the arithmetic accuracy of partial product perforation and prove that it delivers a bounded and predictable output error. Error analysis is not bound to specific multiplier architecture and can be applied with error guarantees to every multiplication circuit regardless of its architecture that compared with the respective exact design, the partial product perforation. Index Terms: Approximate Arithmetic Circuits, Approximate Computing, Approximate Multiplier, Error Analysis & Low Power