Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects

The main aim of this project is to increase the data rate communication between a CPU and a DRAM to above 6.5 GHz by optimization of the Printed Circuit Board (PCB) interconnections (these interconnections include vias, transmission lines and steps), as it's shown in Figure I. The modeling has been performed using the Electro-Magnetic (EM) simulator HFSS (High Frequency Structure Simulator), a 3D full-wave electromagnetic field software that can be used in circuit, high frequency, signal integrity, and electromechanical simulations, up to 100GHz. The modeled passive components have been used in the optimization of the Bit Error Rate (BER) and eye-diagram of the total system, including the parasitic elements of the CPU and DRAM packages by using HSPICE and ADS simulators. In addition, a complete library of these passive structures has been prepared.Pleite Moreno, C. (2011). Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects. Universitat Politècnica de València. http://hdl.handle.net/10251/11506Archivo delegad