Analysis and Design of Decision Feedback Equalizers for Bitrates of 10 Gbps and Beyond in Submicron CMOS

A guideline on how to design and specify a Decision Feedback Equalizer (DFE) for bitrates of 10 Gbps and Beyond. First, this work provides a classification of the state of the art for Decision Feedback Equalizers. Second, this work provides insight about the behaviour of a DFE with increasing number of taps and channel length with measurements done with a state of the art Digital Spectrum Analyser. It also includes a Two-Tap adaptive DFE behavioural model developed by the author of this report. A comparison within the impulse response, the Digital Spectrum Analyzer and the taps obtained with the behavioural model is also developed on this report. Third, on a circuit level perspective, this work exposes the pros and cons of implementing the DFE with different kind of summers and it proposes two unexplored alternative summers to achieve Decision Feedback Equalizer. At the end of this report, a final implementation for the target Clock Data Recovery is done with state of the art performance for a Tenth-Rate DFE. The recommendations on implementing the DFE, how to make it adaptive and all the relevant conclusions are exposed in the last chapter of this report.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc