Power efficient digital correlator in the scope of an UWB baseband design

Ultra Wideband (UWB) radio represents a promising way of communication for low power applications in interference-prone environments. For achieving a low power solution the digital baseband architecture needs to be carefully optimized to reduce the total power consumption. Particularly for the computationally intensive synchronization phase that detects UWB signals in noisy input data, low-power correlation architectures are crucial. In this thesis, a low power exploration is performed at different levels of abstraction. The architecture of the correlator is designed and optimized to support several modes of operations efficiently. Deviating from a memory dominant design, our improved architecture is based on circular register buffer and a corresponding partitioning method. The impact of biased representation is studied in terms of power and area. The possibility and the influence of voltage reduction is also investigated by changing to the Lvt cells and pipelining the critical path. Our design is implemented and simulated in a Cadence based design flow, targetting 90 nm process technology. Experimental results show that, compared to 'standard' design, the proposed correlator can achieve up to 2x total power reduction with only 10\% overhead on area.Embedded SystemSoftware and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc