Testability and Fault Tolerance for Emerging Nanoelectronic Memories

Emerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candidates to replace the conventional memory technologies such as SRAMs, DRAMs and flash memories in future computer systems. Despite their advantages such as enormous storage capacity, low-power per unit device and reduced manufacturing difficulties, these emerging memories are expected to suffer from high manufacturing defect densities (reducing their quality) and in-field fault rates including clustered faults (reducing their reliability). These defects and faults may occur in any part of the memory system including the memory cell array, peripheral circuits and interconnects. Therefore, developing appropriate schemes to address both quality and reliability challenges is critical for the manufacturability of such devices. This thesis discusses the quality and reliability improvement for nanoelectronic memories. In order to develop effective schemes for quality improvement, first a framework of possible defects within RRAMs has been defined. Thereafter, defect injection and circuit simulation using an electrical RRAM model have been performed. Besides conventional memory faults, simulation results also show the occurrence of unique faults. The detection of the latter faults cannot be guaranteed with conventional memory test approaches as read operations will produce random values. Therefore, Design-for-Testability (DfT) schemes have been introduced to increase the fault/defect coverage at minimum overhead. In addition, as the faults may behave differently subject to process variations, the DfT schemes are made programmable to track the changes in fault behaviors while targeting the unique faults. On the other hand, several fault-tolerant (FT) schemes have been proposed to improve the in-field reliability of nanoelectronic memories. First, two FT schemes based on error correction codes (ECCs) have been introduced to tolerate both random and clustered faults in the memory cell array, while optimizing the area overhead and performance penalty. Second, an on-line masking scheme is combined with one of the proposed FT schemes to tolerate faults both in the decoders and the memory array; the decoding process has been modified realizing even smaller and faster decoding circuit. Third, an interleaving scheme is combined with an ECC to tolerate faults in the interconnects at minor area overhead and performance penalty.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc