A flexible high level modelling methodology for power and energy consumption

With the increasing complexity of current embedded applications, and the mobility required in embedded devices, new approaches are being proposed to optimize the power and the energy consumed by an application, at higher levels of abstraction levels and in earlier stages in a design flow. However, one essential part of a structured and guided optimization process, is the early prediction of the power and energy consumption using only the available information at early design stages. These predictions are used as function costs in optimization algorithms to prune the design space exploration in different design stages. In this thesis we aim to improve the partitioning process of the Delft Workbench design flow, for this purpose, we propose a modelling methodology that can generate power and energy models. The models can provide quantitative data that can be used to guide the decisions made in the partitioning process. The partitioning process in the DWB uses as level of abstraction a function described in a high level language (HLL), such as C-code, and targets heterogeneous architectures. Therefore, the methodology we propose can generate models that predict the power and energy consumed by a kernel when is running in a processing element of heterogeneous architectures, such as a general purpose processor (GPP) or an PPGA. For the validation of this methodology we designed a set of experiment that create models of power and energy consumption for a StrongARM processor (using the Sim-Panalyzer simulator), and a Virtex 5 FPGA (using the xpwr tool of Xilinx). A maximum absolute rooted mean squared error (RMSE) of 60mW was obtained for the power models, and a maximum absolute RMSE of 8.69 x 10^-6 was obtained for the energy models.Embedded SystemsComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc