Architecture-Level Fault-Tolerance Techniques for Biomedical Implants

In this thesis the design and implementation of a new fault-tolerant architecture is described. The design targets both soft and hard faults by implementing a combination of known fault-tolerance tech niques in an efficient way. The proposed architecture allows a trade-off to be made between performance and fault tolerance by means of instruction-level configurability. The design is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that an area and power overhead of roughly 25% and 32%, respectively, are required to implement the techniques on the baseline processor. The main overheads of the architecture are performance (up to 106%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is set and therefore the energy consumption does not increase linearly with a higher execution time. It is shown that test sequences can effectively be scheduled during program stalls, and that nearly 100% of all soft faults are tolerated by using instruction duplication. The main advantages of using our techniques are the flexibility to make a trade-off between the overheads and the required degree of fault tolerance, the high portability of the used techniques and the small increase in area and power consumption.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc