Reordering DRAM Requests for Improved Bandwidth Utilization

The performance gap between processors and memory has grown larger and larger in the last years. With the emergence of the multicores this problem is additionally accelerated. Stalling row changes in the DRAM increase this gap even more, because the maximum theoretical bandwidth cannot be reached. The solution that is proposed in this thesis is to reorder the requests originated by multiple processing elements inside the memory controller. More data is accessed in burst mode and less stalling row changes are needed when the requests are reordered. The proposed memory controller has a modular setup and does not require any changes of the CPU or the executed software. A few reordering policies have been considered, but one has been implemented as it showed the best expected results in the preliminary analysis. The speed-up that is obtained by reordering requests varies, but is up to 1.58 for a 3D-FFT and 1.40 for a Conjugate Gradient (CG) workloads with just 64 entries in the sorting array. Power analysis on the DRAM and memory controller shows that the activation power of the DRAM is lowered up to 40% because of the reordering. The total energy that is necessary for each application is reduced with a maximum energy saving of 26.6% for the 3D-FFT and 13.2% for the CG application. This shows that the bandwidth utilization of the DRAM interface is increased while saving energy by using reordering of requests.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc