With the development of the technology, today's digital systems' growing design complexity has outpaced the traditional RTL design flow. The manual steps of micro-architecture definition, hand written RTL, simulation, debug and area/speed optimization through RTL synthesis are becoming more and more time consuming that gives the call of higher level abstraction in digital design. Catapult C synthesis tool, a C/C++ based hardware synthesizer, was released by Mentor Graphics as a solution of high complex digital system design. With this tool, designers are able to describe a complex system in a more productive abstraction level and Catapult C will generate an accurate RTL description turned to the target technology. This thesis presents a pra...
International audienceThis paper presents a methodology to specify from a high-level data-flow descr...
State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low p...
International audienceIn this work we attempt to compare three distinct hardware design approaches: ...
With the development of the technology, today’s digital systems’ growing design complexity has outpa...
Due to copyright restrictions, the access to the full text of this article is only available via sub...
High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL)...
High-level synthesis (HLS) and register transfer level (RTL) are two popular methods to design FPGAs...
We present a VLSI synthesis environment dedicated to the design of image processing architectures. T...
High-level synthesis is by many seen as the next step in the ever-increasing abstraction levels of d...
With increasing FPGA chip density, it is possible to implement more sophisticated algorithms on FPGA...
FPGAs are an attractive platform for applications with high computation demand and low energy consum...
Abstract Much eort in RTL design has been devoted to developing \push-button" types of tools. H...
Field programmable gate arrays (FPGAs) have been extensively used to accelerate numerical intensive ...
The growing complexity of signal processing algorithms and platforms poses significant challenges to...
The purpose of this thesis is to study the methodology of behavioral synthesis and evaluate its usef...
International audienceThis paper presents a methodology to specify from a high-level data-flow descr...
State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low p...
International audienceIn this work we attempt to compare three distinct hardware design approaches: ...
With the development of the technology, today’s digital systems’ growing design complexity has outpa...
Due to copyright restrictions, the access to the full text of this article is only available via sub...
High-level synthesis (HLS) tools greatly reduce the effort required in Register Transfer Level (RTL)...
High-level synthesis (HLS) and register transfer level (RTL) are two popular methods to design FPGAs...
We present a VLSI synthesis environment dedicated to the design of image processing architectures. T...
High-level synthesis is by many seen as the next step in the ever-increasing abstraction levels of d...
With increasing FPGA chip density, it is possible to implement more sophisticated algorithms on FPGA...
FPGAs are an attractive platform for applications with high computation demand and low energy consum...
Abstract Much eort in RTL design has been devoted to developing \push-button" types of tools. H...
Field programmable gate arrays (FPGAs) have been extensively used to accelerate numerical intensive ...
The growing complexity of signal processing algorithms and platforms poses significant challenges to...
The purpose of this thesis is to study the methodology of behavioral synthesis and evaluate its usef...
International audienceThis paper presents a methodology to specify from a high-level data-flow descr...
State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low p...
International audienceIn this work we attempt to compare three distinct hardware design approaches: ...