Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS

WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access. To anticipate the future demands on WiMAX technology, we proposed an ADPLL (all-digital phase locked loop) solution for the WiMAX system. The developed ADPLL system has targeted frequencies from 2.3 GHz to 2.7 GHz and from 3.3 GHz to 3.8 GHz for low band and high band, respectively. In this approach, an ADPLL replaces the conventional RF synthesizer based on charge-pump architecture. There are three main components of the ADPLL system. One of them is the time-to-digital converter (TDC) system. A TDC in state-of-the-art 40 nm CMOS technology for WiMAX ADPLL system is chosen and presented in this thesis. The TDC architecture is based on a pseudo-differential structure. This architecture utilizes an inverter as a delay element and a sense amplifier flip-flop as a time comparator. In comparison, the two other TDC architectures evaluated in this thesis (two-dimensional Vernier algorithm TDC and time-windowed TDC) have very complex architectures and complex calibration methods, while the chosen TDC architecture has a simple calibration method. Moreover, this pseudo-differential TDC can meet the time resolution required by the WiMAX ADPLL system. The TDC system has been tested on a 1.2 V power supply, 33.868 MHz frequency reference clock FREF and with 4.25 GHz frequency of CKV. It is found that the power consumption is about 2.99 mW without a clock gating scheme. Moreover, it is expected that the power consumption can be reduced to 0.78 mW with a clock gating scheme. The INL and DNL of the TDC are lower than 0.4 LSB. The measured TDC resolution is around 10.84 ps - 12.55 ps. In the worst case condition, the TDC resolution of 12.55 ps will give an in-band phase noise better than the limit , which is -95 dBc/Hz as required by the WiMAX ADPLL System. The TDC core layout has an area of only 125 x 11 ?m2.Profile RF Analog Circuit DesignMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc