Timing-Driven chip design

The design scale of Integrated Circuits (ICs) is increasing exponentially according to Moore's law, approaching 1,000,000,000 transistors in the coming years. Unfortunately, this increase in scale has made certain parasitics - most notably the wire delay - more prominent than in older process generations. The actual placement of the components determines the length of the wires, and with that it sets the amount of the wire delay. This parasitic delay dominates the speed and quality of the result as wires get relatively longer. Current methodologies initially ignore those wire delays as they are not known until the end and at check for timing at the end of the flow. An iterative approach is used to go back to higher levels of design and try to fix this problem. However this is a more and more time consuming approach and convergence is not guaranteed. The main idea of this thesis is to plan the critical wires beforehand. A stepwise refinement paradigm for long wires called "wire planning" is derived. A budgeter to distribute delay between wires en logic is presented which is able to handle the usual exponential number of paths. Also a modified constant delay synthesis approach is shown to be able to provide the optimal solution according to the budgets by efficiently exploring and trade-off a larger search-space. The results of this technology mapper are superior compared to the traditional approaches.Electrical Engineering, Mathematics and Computer Scienc