Digital Cartesian feedback linearization of power amplifiers

The efficient use of the power budget in mobiles and small satellite applications is of primary importance because of the reduced size of the power sources. The limited power supply has to be spent wisely. In a transmitter, the power amplifier is the main consumer of that budget, which is why it has to be as efficient as possible. Unfortunately, high efficiency in power amplifiers is strongly related to non-linearities and hence distortion. However, several techniques help to improve the linearity of the power amplifier. One of the most powerful means to linearize a system is using negative feedback. In this work the analysis of a mixed-signal Cartesian feedback is carried out. Cartesian feedback offers two challenges: stability and phase shift. In a feedback system with a time delay in the loop, instability is likely to happen. Phase shift is the result of the time delay in the loop and non-linearities of the power amplifier. First a model of the mixed-signal system is proposed, and the stability of the system is analyzed. Second, a model of the phase shift is proposed, and the conditions under which it can be reduced are given. The model is implemented in the digital domain. In order to realise this a design consisting of a phase shift detector, a signal rotation and a magnitude computation was created in VHDL and then synthesized, while targeting FPGA and 90nm CMOS technology. An FPGA implementation shows a power consumption of 33.31[mW] for a total budget of 1.7[W] (1.96% of the total budget). The system reaches a 60° of phase margin with a loop gain of 10, for a bandwidth of 9.6[kHz]. The results show that it is possible to improve linearity at the expense of bandwidth when using Cartesian feedback.MicroelectronicsElectrical EngineeringElectrical Engineering, Mathematics and Computer Scienc