A power-aware fault-tolerant hardware system for a custom reconfigurable platform

Electronics systems in deep-submicron era face many new challenges. Increased intricacy of the manufacturing process will likely to increase the manufacturing defect while testing of those effect will be very challenging. Smaller feature size will also face new reliability issues due to phenomenas such as Joule heating and electromigration. Furthermore, chances of temporal defects, namely soft-errors, or Single Event Fault (SEU) will increase because the critical charge, the charge required to flip a logical value in flip-flops decreases with technology scaling. Power consumption is another issue that is ever greater in electronics design. Technical, financial, and ecological concern all require devices that consumes as small amount of energy as possible. The Ubichip, a bio-inspired reconfigurable VLSI developed in PERPLEXUS European project has attributes such as dynamic self replication and dynamic routing capability, both of which may help develop a system to increase reliability while addressing the power consumption issues. The author has designed a power aware fault tolerant system based on the Triple Modular Redundancy (TMR) fault tolerant strategy to be implemented on Ubichip. The system also controls the number of functional unit to regulate the overall system power consumption. This report describes the design, implementation, and simulation of the fault-tolerant system.CASMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc