Exploring and implementing a User Datagram Protocol/Internet Protocol stack within a small Field Programmable Gate Array

This thesis is part of the Arachne project which focusses on novel processor architectures that enable an ubiquitous and unobtrusive communication environment. Nowadays, the Internet provides many services of which some are envisioned to be utilized by stand alone devices. Access to those services requires an Internet Protocol stack (IP) implementation. Current solutions with IP functionality in reconfigurable hardware focus on high-end members of FPGA families and often require an embedded RISC processor. The major goal of this project is to implement a design on a low cost FPGA, while leaving space available to run an application alongside. The system is designed around the Xilinx Picoblaze, where additional modules are implemented to improve the performance and provide the required functionality. The experimental results show that such a design is feasible.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc