Run-Time Partial Reconfiguration on the Virtex-II Pro

Reconfigurable Computing entails the utilization of a general-purpose processor augmented with a reconfigurable hardware structure (e.g. a field-programmable gate array). Normally, a complete reconfiguration is needed to cha nge the functionality of the FPGA even when the change is only minor. Moreover, the complete chip needs to be halted to perform the reconfiguration. Dynamic partial reconfiguration (DPR) enables the possibility to change parts of the hardware while other parts of the FPGA remain in use. In this paper, we propose an additional solution to perform dynamic partial reconfiguration by providing a methodology to generate bit-streams for removal of old hardware, and placement and routing of new hardware within an FPGA. This means that functionality can be removed from, and additional functionality can be added to the FPGA at any location. Our solution is able of connecting the additional functionality to the already running parts of the chip. More over, bus macros are no longer necessary and no synthesis is needed to implement the routing. We implemented our solution on a Xilinx Virtex-II Pro series FPGA, specifically the XC2VP30 on the XUP board, and demonstrated that the solution works.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc