Low power techniques for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tri-state on-chip buses with level or transition signaling. At the circuit level we propose novel line drivers using charge recovery which can reduce power dissipation for large loads by 20-30%. Both a single-ended and a differential driver, using two-step charging and discharging of the line capacitances, are proposed. The circuits are approximately twice as large and slightly slower than equivalent inverter chains and can be used either as bus line drivers or as clock drivers