Integrated High-Speed DSP for All-Digital RF Transmitters

During the recent years, the design of integrated RF transceivers has been shifting towards the digital domain. There are two main motivations behind this change. First, the reconfigurability needed in 4G and 5G wireless communication calls for A/D and D/A conversion as close to the antenna as possible. Second, the advance of deep-submicron CMOS processes poses new design challenges for traditional analog topologies, whereas digital circuits typically benefit from decreasing linewidth and supply voltage. This dissertation presents advances related to all-digital RF transmitters, with special focus on the cartesian and outphasing architectures. Specifically, this work attempts to extend the share of transmitter functionality that is implemented using integrated digital signal processing (DSP). The main motivation in the research of DSP-based solutions is that, besides exploiting all the benefits of nanoscale CMOS, they also take advantage of highly automated standard design methodologies, thus enabling straightforward design reusability. The research work is demonstrated with two integrated circuit (IC) implementations and seven scientific publications. In the context of all-digital cartesian transmitters, this dissertation focuses on the replacement of the traditional analog filters for D/A reconstruction and out-of-band emission attenuation by means of DSP circuits. The D/A reconstruction filter is replaced by a programmable interpolation chain, which is specifically optimized for 4G mobile transmitters. Furthermore, a new DSP technique based on delta-sigma modulation and mismatch-shaping is proposed for receive band noise attenuation. The latter technique is experimentally verified for a prototype 4G transmitter IC fabricated in 28nm CMOS, with measurement results demonstrating up to 20 dB noise attenuation at a programmable 30-400 MHz duplex distance. All-digital outphasing transmitters push the D/A conversion even closer to the antenna, by utilizing time-domain processing of rail-to-rail signals up to the power amplifiers. This dissertation presents a new delay-line phase modulator architecture, which improves the modulation linearity by performing DSP-intensive first-order hold phase interpolation. Measurement results on a prototype multilevel outphasing transmitter IC, fabricated in 28nm FDSOI CMOS, demonstrate that this concept enables up to 400 MHz instantaneous RF bandwidth, which is a 10x improvement compared with the state-of-art