RECONFIGURABLE DIGITAL FUZZY LOGIC CONTROL PROCESSOR ON PROGRAMMABLE LOGIC DEVICE

This monograph book presents the design of digital fuzzy logic controller (FLC) processor and its implementation on a Complex Programmable Logic Device (CPLD). The FLC processor is modeled and designed using Very-High-Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). The modeling, simulation and configration on the CPLD device is made using a software tools (integrated development environment ??? IDE) from Altera i.e. MAX+PLUS II. The book proposes the two-input single-output Programmable FLC with parallel architecture. The Programmable FLC can be programmed in terms of its 6-input membership functions and forms, 9-rule of the fuzzy\ud implication or inference, and its 3-output singleton consequences. Thus this FLC processor can be applied for wide-range control applications. The FLC circuit is\ud implemented on EPF10K70RC240-4, a FLEX10K CPLD device from Altera containing over 70,000 logic gates. The implementation result shows that it requires 98 % of total logic cells on the device. In-circuit testing presents that the FLC processor can be operated at clock frequency of 1.573 MHz. Using six-stage datapath pipeline latency, input-output operation delay time is about 3.1786 us