International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed
Semiconductor memories are an inherent part of many modern electronic systems. Due to the fast devel...
Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, s...
Many scientists and engineers are striving to decrease the die size and lower the development cost s...
International audienceThe research and prototyping of new memory technologies are getting a lot of a...
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. T...
International audienceThe power and reliability issues of today’s memories (static and dynamic RAMs)...
This paper introduces a new test approach: device-aware test (DAT) for emerging memory technologies ...
Semiconductor memories have been always used to push silicon technology at its limit. This makes the...
Emerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candi...
Spin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as one of the most promisi...
In this thesis, we study the problem of faults in modern semiconductor memory structures and their t...
Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate ...
In recent years, embedded memories are the fastest growing segment of system on chip. They therefore...
International audienceSpin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising non-volatile memor...
Due to rapid and continuous technology scaling, faults in semiconductor memories (and ICs in general...
Semiconductor memories are an inherent part of many modern electronic systems. Due to the fast devel...
Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, s...
Many scientists and engineers are striving to decrease the die size and lower the development cost s...
International audienceThe research and prototyping of new memory technologies are getting a lot of a...
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. T...
International audienceThe power and reliability issues of today’s memories (static and dynamic RAMs)...
This paper introduces a new test approach: device-aware test (DAT) for emerging memory technologies ...
Semiconductor memories have been always used to push silicon technology at its limit. This makes the...
Emerging nanoelectronic memories such as Resistive Random Access Memories (RRAMs) are possible candi...
Spin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as one of the most promisi...
In this thesis, we study the problem of faults in modern semiconductor memory structures and their t...
Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate ...
In recent years, embedded memories are the fastest growing segment of system on chip. They therefore...
International audienceSpin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising non-volatile memor...
Due to rapid and continuous technology scaling, faults in semiconductor memories (and ICs in general...
Semiconductor memories are an inherent part of many modern electronic systems. Due to the fast devel...
Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, s...
Many scientists and engineers are striving to decrease the die size and lower the development cost s...