Design and Implementation of 94 GHz CMOS Down-Conversion Mixer Using Current-Bleeding and Modified Derivative Superposition (DS) Techniques

[[abstract]]本論文主要以台積電90奈米&40奈米CMOS製程來實現W-Band降頻混波器、低雜訊放大器。此研究論文主要由以下四個部份構成: 第一部份為操作於W-band之氣象觀測雷達之具高增益的CMOS 降頻混波器。此降頻混波器包含：一雙平衡式吉伯特單元，其整體架構之轉導級中心加入電流注入架構使其能夠提升轉換增益之外，亦能讓電流再利用達到降低功率損耗，以及使用了修正導數疊加技術，用以平衡因提高轉換增益所導致線性度下降的缺點，另外採用頻率94GHz換衡器(Marchand Balun)用於將LO及RF輸入訊號由單端轉雙端 第二部分為操作於W-band之接收機的正迴授低雜訊放大器，此低雜訊放大器為二級放大，於第一級主要放大級中採用了穩定正迴授的架構，藉由調整正迴授結構內的電容容值來提升增益，同時調整電感感值來保持高穩定性；第二級放大採用疊接組態，用以平衡正迴授帶來的低隔離度缺陷。因為整體電路只使用二階架構，消耗功率、晶片面積均同時獲得減少。 第三部分為應用於180GHz氣象雲雷達之CMOS降頻混波器，此混波器採用40奈米製程，在架構上使用了一雙平衡式吉伯特單元、PMOS交叉耦合對及NMOS電流注入架構，並且在轉導級與開關級中間加入Inter-Stage Inductor來將寄生電容共振開路，有效降低雜訊。另外採用頻率188 GHz換衡器(Marchand Balun)用於將LO及RF輸入訊號由單端轉雙端 第四部分為結論，總結以上三份晶片之研究成果與數據。[[abstract]]This thesis mainly utilizes standard TSMC 90 nm CMOS process technology to implement down-conversion mixers and positive feedback low noise amplifier for W-band. The thesis is composed of four sections: In the first section, the high gain CMOS down-conversion mixer which is implemented in meteorological observation radar in W-band. This mixer is consisted of a double balanced mixer, a current bleeding technology and modified derivative superposition (DS) techniques. A current bleeding schematic is composed of a pair of PMOS and it will inject current into tranconductance stage which can transform voltage to current. In addition to raise the conversion gain, this method can reuse current to decrease power consumption. And using modified derivative superposition (DS) techniques will get better linearity. A 94 GHz Marchand balun for converting the single LO input signal to differential signal, and another Marchand balun for converting the single RF input signal to differential signal. Generally speaking, this work can demonstrate a high gain, great linearity and low power consumption mixer. In the second section, a positive feedback low noise amplifier working in W-band is implemented. This low noise amplifier is 2nd stage. There is an architecture using stable positive feedback applies in 1st stage. According to the formulation of feedback gain, it shows that the positive feedback architecture will increase gain effectively and gain can be controlled by capacitance. Although the stability will be influenced, it can be adjusted the inductance value to maintain high stability. The 2nd stage uses cascade structure. The purpose of this structure is to increase isolation. Because of using 2nd stage only, the power consumption and chip area will be decreased both. In the third section, a 180 GHz CMOS down-conversion mixer is implemented. This mixer adpots 40nm process. The architecture of this work adopts a pair of Gilbert cell, PMOS cross-coupling and NMOS current injection architecture. And there is an Inter-stage inductor which will resonant parasitic capacitance to reduce the noise figure. In addition, there is a 188 GHz Marchand balun for converting the single LO input signal to differential signal, and another Marchand balun for converting the single RF input signal to differential signal. Generally speaking, this work can demonstrate a high gain, great linearity and low power consumption mixer. The last part is conclusion, it shows that all performance of these chips.[[note]]碩