Effects of Non-ideal Switches on Speed of SC Integrator

This paper presents a method with which the switches in the classical switched capacitor(SC) integrator can be optimized to achieve smallest layout area in the meanwhile maintaining circuit speed within demand. After introduction of structure and function of the SC integrator that is composed of capacitors, switches and op amp, the reason why switches involved should be optimized is given that is due to the noneideal factors of switch. The method at first calculates the maximum on-resistance of a CMOS switch in accordance with speed specification, then the width and length of channel of the PMOS and NMOS involved in a CMOS switch are obtained through numerical simulations by HSPICE. The results show that a switch should be designed with 0.3μm/0.35μm for PMOS and NMOS, respectively, to achieve smallest layout area for the SC integrator implemented by TSMC 0.18 um Mixed Signal SALICIDE technology