Part 1: Systems, Networks and ArchitecturesInternational audienceHybrid cache architecture (HCA), which uses two or more cache hierarchy designs in a processor, may outperform traditional cache architectures because no single memory technology can deliver the optimal power, performance and density at the same time. The general HCA scheme has also been proposed to manage cache regions that have different usage patterns. However previous HCA management schemes control data placement at cache set level and are oblivious to software’s different power and performance characteristics in different hardware cache regions. This hardware-only approach may lead to performance loss and may fail to guarantee quality of service. We propose a new HCA appr...
International audienceThis chapter presents a technique for reducing energy consumed by hybrid cache...
Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byt...
Journal ArticleConventional microarchitectures choose a single memory hierarchy design point target...
Journal ArticleIn future multi-cores, large amounts of delay and power will be spent accessing data...
Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum ...
One newly designed hierarchical cache scheme is presented in this article. It is a two-level cache a...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
This thesis studies the use of software methods to improve memory performance in a heterogeneous cac...
The cost of a cache miss depends heavily on the location of the main memory that backs the missing l...
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memo...
STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based...
Cache memory is one of the most important components of a computer system. The cache allows quickly...
As cache hierarchies become deeper and the number of cores on a chip increases, managing caches beco...
Embedded systems are getting popular in today’s world. They are usually small and thus have a limite...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
International audienceThis chapter presents a technique for reducing energy consumed by hybrid cache...
Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byt...
Journal ArticleConventional microarchitectures choose a single memory hierarchy design point target...
Journal ArticleIn future multi-cores, large amounts of delay and power will be spent accessing data...
Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum ...
One newly designed hierarchical cache scheme is presented in this article. It is a two-level cache a...
Memory (cache, DRAM, and disk) is in charge of providing data and instructions to a computer\u27s pr...
This thesis studies the use of software methods to improve memory performance in a heterogeneous cac...
The cost of a cache miss depends heavily on the location of the main memory that backs the missing l...
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memo...
STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based...
Cache memory is one of the most important components of a computer system. The cache allows quickly...
As cache hierarchies become deeper and the number of cores on a chip increases, managing caches beco...
Embedded systems are getting popular in today’s world. They are usually small and thus have a limite...
The performance gap between processor and memory continues to remain a major performance bottleneck ...
International audienceThis chapter presents a technique for reducing energy consumed by hybrid cache...
Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byt...
Journal ArticleConventional microarchitectures choose a single memory hierarchy design point target...