Architectural Considerations for a Shared Out-Of-core Dynamically Reconfigurable Fabric

Dynamically reconfigurable systems are systems that incorporate some degree of hardware programmability (usually in the reconfiguration of basic-block communication pathways). Although the concept has a long pedigree, there has been a significant amount of recent work in the field motivated in part by modem high-density FPGAs and power-aware systems in general. Application areas include a wide variety of special-purpose and on-demand adjunct support to the processor including DSP, multimedia, embedded (control), cryptography and general scientific computing. The dominant current model offering Dynamically Reconfigurable Support (DRS) to the processor is typically expressed in terms of some variety of off-chip reconfigurable fabric. Alternative models bring DRS closer to the processor core, either as a resource in-core or out-of-core. In-core DRS may make sense for monocore systems, but the relatively low utilization of DRS mitigates for an out-of-core (shared) solution for the multicore CMP. We take as a model a dynamically reconfigurable fabric and examine initially design considerations from a simple monocore environment with configuration caching, configuration speculation, and access protocols. This leads to suite of models for a multicore system with gradually less-restrictive access protocols to a completely shared DRS. Three models for sharing DRS among multicore processors are presented. These models reflect design choices driven by extant multithreading architectures. The thesis explores a reservation/dispatcher architecture which permits multiway Out-Of-Order access to the DRS and a sample implementation is given. Finally, the thesis addresses the problem of assessment for a DRS, and provides a few simple, exploratory metrics.